Požadujeme
- Bachelor or Master’s Degree in Electrical Engineering, Computer Engineering or relevant
- Experience in developing and implementing RTL for any FPGA platform (VHDL, Verilog, System Verilog, OpenCL)
- Experience in programming in C/C++
- Solid understanding of TCP/IP networks
- Knowledge of Linux
- Knowledge of IDE and other design tools (GIT, SVN, etc.)
- Ability to work in team
- English - ability to communicate with peers, customer and management
- Advantageous - experience in any of the following would be plus
- CPU/GPU architecture, OpenCL, SoC, ASIC
- image processing, data compression, cryptography, multithreaded applications
- QoS, routing, switching
- PERL, Bash, assembly language
Nabídka
- long-term contract
- working with the cutting-edge technologies
- international projects
- daily usage of English
- flexible working hours
- occassionally home-office
- initial training (depending on project EU, USA)
- technical trainings
- language courses
- refreshment at work free
- extra holidays
- meal vouchers
- pension / life insurance
- company events
- cafeteria
Pracovní náplň
- Design, development and debugging of RTL code/IP in FPGA
- Development of auxiliary and testing SW
- Design benchmarking
- Assignment to a particular project depends on experience / knowledge
- Occasionallly travelling to EU / USA, mostly at the project startup
- Initial training abroad lasting several weeks
- Communication with local/remote team and customers
Kontakt - zadavatel pozice
Jobs Contact Personal, s.r.o.Odpovědná osoba: Klára Gazdíková Telefon: Zobrazit tel. číslo Mobil: Zobrazit tel. číslo Email: zaslat email Web: https://www.jobscontact.cz/prace Facebook: https://cs-cz.facebook.com/jobscontact/ LinkedIn: https://cz.linkedin.com/company/jobs…
Adresa:
Křenová 531/69a
Brno
602 00
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